Field of the Invention
The present invention relates to an image forming apparatus. In particular, the present invention relates to an image forming apparatus that includes a master CPU and a slave CPU controlling an operation of a prescribed load based on a data from the master CPU.
Description of the Related Art
Conventionally, among image forming apparatuses, there are laser beam printers that form an image on a transfer material by performing a scan with a laser beam.
FIGS. 15A to 15B are diagrams illustrating schematic configurations of conventional laser beam printers. FIG. 15A illustrates a configuration that connects one optional cassette to an image forming section 2. FIG. 15B illustrates a configuration that connects a plurality of optional cassettes to the image forming section 2.
An image forming apparatus 1, such as a laser beam printer, includes the image forming section 2 that forms an image on a transfer sheet 6 by an electrostatic recording system.
The image forming section 2 receives an on/off signal of a laser beam from an image expanding section (not illustrated), drives the laser beam based on the on/off signal and thereby forms the image on the transfer sheet 6. The image forming section 2 includes a cassette tray 32 for mounting transfer sheets. An internal transfer sheet transportation system (not illustrated) transports the transfer sheet picked up from the cassette tray 32. A motor (not illustrated), which may be a stepping motor, for driving the transfer sheet transportation system is controlled by a master CPU 18.
The image forming section 2 detachably includes an optional cassette 17 including a sheet supply section 16. The optional cassette 17 causes the transfer sheet transportation system (not illustrated) internally included in the sheet supply section 16 to transport the transfer sheet 6 stored in the cassette tray 33 to the image forming section 2, to which the optional cassette 17 is attached. A slave CPU 19 in the sheet supply section 16 causes a communication unit (not illustrated) to receive and transmit an instruction by the master CPU 18, and controls the sheet supply section 16 according to a program stored in a ROM (not illustrated), which may be embedded in the slave CPU 19 or externally equipped. The master CPU 18 controls the image forming section 2. The slave CPU 19 controls the sheet supply section 16.
Conventionally, one of a start-stop synchronization serial communication and a clock-synchronized serial communication is often employed, as a typical communication unit, for transmitting and receiving a data between the master CPU 18 and the slave CPU 19. Hereinafter, description will be made using an example of the clock-synchronized serial communication.
FIG. 16 illustrates a schematic connection diagram for schematically illustrating communication between the master CPU 18 and the slave CPU 19.
A communication unit 20 includes a clock signal line (CLK) 305 transmitting a clock signal output from the master CPU 18, a command signal line (CMD) 306 transmitting a command signal synchronized with the clock signal output from the master CPU 18, and a status signal line (STS) 307 transmitting a status signal output from the slave CPU 19.
The status signal is transmitted in synchronization with the clock signal of the clock signal line (M-CLK) 305. The status signal line (STS) 307 is not limited to one-directional communication from the slave CPU to the master CPU 18, but may be two directional. Further, the status signal line (STS) 307 may transmit the status signal into which an output from a sensor provided at the optional cassette 17 is interleaved.
FIG. 17 illustrates a timing chart of the clock signal (M-CLK signal), the command signal (CMD signal) and the status signal (STS signal).
The master CPU 18 transmits the command signal (CMD signal) synchronized with the clock signal (M-CLK signal) to the slave CPU 19. The slave CPU 19 returns the status signal (STS signal) synchronized with the clock signal (CLK signal) to the master CPU 18. Accordingly, communication between the two CPUs is established.
As illustrated in FIG. 16, the master CPU 18 operates in synchronization with a clock M-CLK21 from a clock circuit 22 for the master CPU. On the other hand, the slave CPU 19 operates in synchronization with a clock S-CLK23 from a clock circuit 24 for the slave CPU.
The clock circuit 22 for the master CPU often employs a quartz oscillator, which is a clock oscillation circuit with high accuracy, in order to control an electrostatic latent image in the image forming section 2 and transportation of a transfer sheet.
When an error occurs in rotation rate of an optional motor (not illustrated) driven by a driving from the slave CPU 19, an error also occurs in transfer sheet transportation speed of the optional cassette 17, as a matter of course. When the error in transfer sheet transportation speed occurs, the transfer sheet transported from the optional cassette 17 is not smoothly passed at a transportation roller of the image forming section 2. Accordingly, the transfer sheet may be torn or contrarily buckled, and cannot be transported. Therefore, an appropriate image forming operation cannot be performed.
Thus, in order to improve accuracy in transfer sheet transportation speed at the optional cassette 17, the clock circuit 24 for the slave CPU often employs a quartz oscillator, which is a clock oscillation circuit with high accuracy.
FIG. 15B illustrates a configuration where optional cassettes 17-1 to 17-3 have a multistage configuration, sheet supply sections 16-1 to 16-3 are configured in a multistage structure and slave CPUs 19-1 to 19-3 are cascadingly connected to a master CPU 18. Here, an example where the sheet supply sections 16-1 to 16-3 employ a three-stage configuration. The configuration is not limited to the three-stage configuration, but may be a configuration whose number of stages is two or more than three.
In this multistage configuration, the master CPU 18 transmits a transmission data 18-1 to the slave CPU 19-3 at the bottom stage. The slave CPU 19-3 picks up a data related to the slave CPU 19-3 from the received transmission data, performs a transporting operation according to a program stored in a ROM (not illustrated) and subsequently transmits a transmission data 18-2 to the slave CPU 19-2 at the directly upper stage.
The slave CPU 19-2 picks up a data related to the slave CPU 19-2 from the transmission data, performs a transporting operation according to a program stored in a ROM (not illustrated) and subsequently transmits a transmission data 18-3 to the slave CPU 19-1 at the directly upper stage.
The slave CPU 19-1 picks up a data related to the slave CPU 19-1 from the received transmission data, performs a transporting operation according to a program stored in a ROM (not illustrated) and subsequently transmits a transmission data 18-4 to the master CPU 18 at the directly upper stage.
In a case where optional units, such as a double-sided transportation unit, an optional cassette unit and an optional envelop unit, are caused to perform an identical operation at the same time, if an option communication unit performs communication operations to the respective optional units in a time series manner and thereby causes the units to perform operations, the operations deviate from each other. In order to address this problem, an image forming apparatus is known that includes a control of separately supplying signals to respective optional units and a control of supplying a common signal to the optional units and changes signal supplying modes according to a state of an engine controller.
The signal supplying mode includes a mode of outputting a prescribed signal to each of the optional units in a time series manner and a mode of concurrently outputting signals specific to the respective optional units to the same units (Japanese Patent Application Laid-Open No. H09-193508).
In recent years, technological innovation in CPU for mechatronics control has remarkably improved. One-chip CPUs embedded with an inexpensive RC oscillator circuit have been provided.
The RC oscillator circuit configured in a semiconductor such as a CPU is inferior in accuracy to a quartz oscillator and a ceramic oscillator. However, control elements that do not require high oscillation accuracy can employ the RC oscillator. This configuration negates the need to externally attach one of an oscillator and an oscillating element to the CPU, thereby providing an advantage that allows a control element to be configured with a simple and inexpensive configuration.
However, in the sheet supply section requiring accuracy in transfer sheet transportation speed, a motor transporting the transfer sheet is driven based on an oscillation period of the oscillator, and the accuracy in transfer sheet transportation speed depends on oscillation accuracy of the oscillator. Therefore, in the image forming apparatus, if the oscillation accuracies of oscillation circuits are different between the image forming section and the sheet supply section provided in the optional cassette, accuracies in transfer sheet transportation speed also differ from each other accordingly. The difference in turn causes a problem in transportation of the transfer sheet. Therefore, the sheet supply section should also employ an oscillator with high oscillation accuracy, as with the image forming section. Accordingly, the advantage acquired by employing the RC oscillator circuit with inferior oscillation accuracy cannot be enjoyed.
Thus, a configuration is required that does not cause difference in accuracy in transfer sheet transportation speed even in a case of employing the RC oscillator circuit with inferior oscillation accuracy as the oscillation circuit for driving the CPU of the sheet supply section in the optional cassette.